Yuheng Yang
Yuheng Yang is a PhD student in electrical engineering and computer science whose research is focused on the development of end-to-end security verification frameworks for hardware designs. With the support of a MathWorks Fellowship, Yuheng will work to bridge the gap between computer architecture and formal verification, making formal tools easily accessible to hardware designers, including tools for both the early and later register-transfer level (RTL) stages. Currently, he is exploring verification techniques targeting RTL implementations. Yuheng’s vision is to innovate verification schemes, achieving better scalability by leveraging architectural insights, so that hardware designers can be involved in the verification loop. To that end, he is designing verification schemes for secure speculation defenses with two objectives: to allow hardware designers to assist the verification process by writing shadow logic machinery interacting with processor logic and to boost the verification scalability by exploring the taint tracking technique. Yuheng’s research could significantly contribute to MathWorks’s HDL tools by improving how the industry approaches hardware design through more effective methods and greater involvement of hardware engineers in the verification process.